1. Technical Field
The present invention relates to integrated circuit verification tools in general, and more particularly, to a method and apparatus for performing equivalence checking on logic circuits. Still more particularly, the present invention relates to a method and apparatus for performing equivalence checking on logic circuit designs having differing clocking and latching schemes.
2. Description of Related Art
During the design stage of integrated circuits, equivalence checking is commonly performed in order to find circuit equivalence between two logic circuit designs. There are many circumstances under which sequential input/output (I/O) equivalence checking on two logic circuit designs having differing clocking and latching schemes are desirable. For example, after a logic circuit design has been remapped to a newer circuit technology, it is very common that the clocking and latching libraries of the newer circuit also need to be changed, especially when the remapping is non-trivial. Also, because the remapping may occur across different hardware description languages, such as changing from Verilog to very-high level description language (VHDL) or vice-versa, it is beneficial to use a sequential equivalence checking tool to ensure that the remapping does not alter the I/O behavior of the logic circuit design.
However, logic circuit remapping tends to pose several challenges to sequential equivalence checking. For example, after remapping had been performed on one of the logic circuit designs, the two logic circuit designs may not be I/O equivalent anymore due to many reasons. One reason being an output transition of a logic circuit design using master-slave pairs can come half a clock period earlier or later than its equivalent circuit design using edge-sensitive registers. Nevertheless, such a difference is not of interest when verifying equivalence because it does not affect the overall design behavior, and the difference is merely an artifact of the chosen clocking and latching scheme and the chosen hierarchy points at which the equivalence check is performed.
Although the above-mentioned problem can be rectified by manually adding a “wrapper” layer of latches to the “faster” logic circuit design to normalize out any mismatches, such a solution has a computational overhead in addition to the practical unattractiveness of manually editing the logic circuit design only for the purpose of equivalence checking. In addition, on a more serious level, the different clocking and latching schemes may destroy a great deal of “signal equivalences” within the two logic circuit designs for the same reason, i.e., internal master-slave pairs update slightly earlier or later than internal registers, causing all gates in the combinational fanout of such elements to mismatch functionally. Since most sequential equivalence checking algorithms rely upon a significant amount of internal gate equivalences for speed and scalability, thus, such characteristic adds an enormous computational overhead to the sequential equivalence checking process. Consequently, it would be desirable to provide all improved method and apparatus for performing equivalence checking on logic circuit designs having differing clocking and latching schemes.